Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, 32-nm Technology Nodes

In this paper, we compare four SRAM circuits. They are the conventional SRAM1, the SRAM2 with power switches on VSS line, the SRAM3 with switches on VDD line, and the SRAM4 with switches on both VDD and VSS lines, respectively. Among the four SRAMs, the SRAM2 shows the smallest amount of leakage, because its subthreshold leakage is most suppressed by its BODY and Drain-Induced Barrier Lowering (DIBL) effects. In addition, the area overheads of the SRAM2, SRAM3, and SRAM4 are also compared thus the SRAM2 being found most favorable in terms of the area penalty. To reduce the oxide-tunneling leakage more, the SRAM5 with precharge voltage lowering is considered in this paper. Compared with the SRAM2 without lowering the precharge voltage, amounts of leakage of the SRAM5 are suppressed by 24.4%, 13.1%, and 4.2%, respectively, at -25°C, 25°C, and 100°C, for the 65-nm node.